Researchers Create a Hybrid Technology | ELE Times

Over the past few decades, the incredible progress made in the electronics industry has been partially driven by innovations at the single-transistor level. A transistor is a semiconducting device that can conduct, insulate and amplify electric current inside electronic circuits. Building faster and smaller transistors has been a primary goal for the semiconductor industry over the past few years.

Metal-oxide-semiconductor field-effect transistors (MOSFETs) are the most conventional and widely used type of transistors. One of their major limitations is their high power inefficiency, which is due to their inability to reduce the voltage supply while simultaneously limiting the off-state leakage current.

A novel and alternative type of device called a tunnel field-effect transistor (TFET) can overcome this limitation by leveraging quantum mechanical tunneling instead of thermionic emission. TFETs, particularly those with an III-V heterostructure, require less than 60 mV of gate voltage swing to induce a variation of one order of magnitude in the drain current at ambient temperatures. Despite their lower power consumption, TFETs have not yet achieved the remarkable speed and energy efficiency of MOSFETs at higher drive voltages.

Researchers at IBM Research Europe and at École Polytechnique Fédérale de Lausanne (EPFL) have recently developed the first silicon-based hybrid device that combines III-V tunnel FETs and conventional MOSFETs.

We demonstrated the first hybrid technology platform combining III-V tunnel FETs and MOSFETs with a scalable process and suitable for large-scale semiconductor manufacturing. Such low-power technology platform paves the way to future energy-efficient electronics, with the ultimate goal of reducing the carbon footprint of the ICT industry.

The new platform developed by Convertino and her colleagues exploits the synergies between tunnel FETs and MOSFETs, as it allows users to implement hybrid logic blocks tailored to the unique specifics of each type of device. In initial evaluations, the scaled III-V hybrid TFET-MOSFET device achieved a minimum subthreshold slope of 42 mV dec⁻¹ for TFET devices and 62 mV dec⁻¹ for MOSFET devices.

Tunnel FETs provide lower leakage and good performance at low voltages levels, while MOSFETs are faster (at the same dimension and bias) and provide greater current drive. The developed fabrication flow is identical for both devices except for a single masking and epitaxy step, opening up for manufacturing of truly hybrid logic blocks. Moreover, our tunnel FETs show record performance at the smallest gate length reported to our best knowledge.

Convertino and her colleagues were the first to effectively demonstrate the integration of an in-plane heterojunction tunnel FET in an advanced hybrid platform using replacement metal-gate and spacer technologies. In the future, the technology they created could enable the development of faster and more efficient electronic devices that combine the advantages associated with TFET and MOSFET transistors.

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